| 摘要 |
PURPOSE: A synchronous DRAM(SDRAM) having the same write latency as a read latency is provided, where a data input/output timing in a read and a write operation is the same as CAS latency. CONSTITUTION: The synchronous DRAM includes: a control signal generation part(350) generating a clock enable signal controlling clock generation and a data input enable signal controlling data input inputted to a data input path in response to a read command signal and a write command signal and a burst command signal and an external clock signal; the first latency delay part(340) generating the second data input enable signal by delaying the data input enable signal for the enable CAS latency value in response to the first or the third CAS latency signal enabled according to a CAS latency of a memory; the second latency delay part(360) generating the second clock enable signal by delaying the clock enable signal for the enable CAS latency value in response to the first or the third CAS latency signal; and a clock generator(330) generating a data clock signal used in synchronizing input data by receiving the first internal clock signal as an input in response to the second clock enable signal. A write CAS latency inputting data after beginning the write command in the data input operation is actually the same as a read CAS latency outputting data after beginning the read command in a read operation.
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