| 摘要 |
PURPOSE: To obtain a highly stable high performance semiconductor device in which finer atterning can be effected while suppressing short channel effect. CONSTITUTION: Impurity concentration in the channel region 30 of an MOS transistor is set higher at the end of a surface depletion layer 26 than on the surface of a semiconductor substrate 20 by providing an impurity concentration profile of linear or higher order function or Gaussian distribution. Since elongation of source and drain depletion layers 27, 28 can be controlled and the depletion layer regions 29s, 29d not contributing to the threshold voltage of a MOS transistor can be minimized, short channel effect is suppressed resulting in a highly stable high performance semiconductor device in which finer patterning can be effected.
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