| 摘要 |
PURPOSE: A method for manufacturing a bit line contact in a DRAM semiconductor device is provided to simplify a manufacturing process, by simultaneously forming a bit line in cell and peripheral regions and a contact. CONSTITUTION: A gate pattern(15) covered with a mask insulating layer(17) and a spacer insulating layer(13) is formed on a substrate(10) where fields are isolated. A selective epitaxial glass(SEG) layer(19) is formed in an active region. The SEG layer formed in the active region of a cell region is preserved, and metal silicide is formed on the SEG layer formed in the active region of a peripheral region. An interlayer dielectric(20) is stacked, and patterned to form a contact hole. A polysilicon layer doped with high density n-type impurities is stacked by a chemical vapor deposition(CVD) method, and is made to remain on the bottom surface of the contact hole by a predetermined thickness. At least a part of the polysilicon layer is formed with metal silicide. A metal bit line is formed while a metal contact is formed.
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