| 摘要 |
PURPOSE: A synchronous memory device is provided to reduce chip design area load and test costs, by controlling to replace an operation of a dual global read input/output line with a write global input/output line together with a single global read input/output line during a bank compress test mode. CONSTITUTION: According to a data bus sense amp, a current mirror type differential amplifier part(50) receives data stored in each of a number of banks(Bank0-Bank3) and amplifies the data. And, a latch part(52) is formed with a RS flip-flop comprising two NAND gates(NAND51,NAND52), and latches a voltage over both ends of output terminals(N1,N2) of the differential amplifier part. The first driver part(54) loads data onto a write input/output line(GW I/O) and its driving is controlled by an assembly of an output terminal(N3) signal of the latch part and a control signal(bct). The second driver part(56) performs a pull-up and a pull-down operation by receiving the output terminal signal of the latch part and the control signal(bct) and thus loads data onto a read single input/output line(GR I/O).
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