| 摘要 |
PURPOSE: A column decoder of a semiconductor memory device is provided to reduce the size of the semiconductor memory device by reducing the size of the column decoder. CONSTITUTION: The column decoder comprises a column decoder(301) and a column selection line driver(305). The column decoder inputs column address signals(DCA01<0>,DCA01<1>,DCA23,DCA45) and outputs column selection line signals(DCA05B<0>,DCA05B<1>). The column decoder comprises PMOS transistors(311,312) and NMOS transistors(321-324). The PMOS transistors and the NMOS transistor(324) are gated by a column address signal(DCA45). That is, if the column address signal(DCA45) is activated as logic high, the PMOS transistors are turned on, and if the column address signal is inactivated as logic low, the NMOS transistor(324) is turned on. The NMOS transistors(321,322) are gated by a column address signal(DCA01), and the NMOS transistor(323) is gated by a column address signal(DCA23). The column address signal(DCA01) is constituted with two signals(DCA01<0>,DCA01<1>). The column selection line signal(DCA05B<0>) is output from a node(N3), and the column selection line signal(DCA05B<1>) is output from a node(N4).
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