发明名称 CHIP SCALE SEMICONDUCTOR PACKAGE
摘要 PURPOSE: A chip scale semiconductor package is provided to be adapted for a multi-pin package by overcoming the limit of a ribbon bonding process to correspond to a fine pitch pad even when a semiconductor chip is smaller than a solder ball array. CONSTITUTION: A semiconductor chip(201) has an insulating layer(210) where respective windows(c) exposing a chip pad to an upper surface of the insulating layer is patterned. A solder mask(204) has a plurality of penetration holes and solder balls(205), covering the semiconductor chip. A metal foil(212) covering the penetration holes is formed in an outer portion covering the semiconductor chip, formed on the back surface of the solder mask having the solder ball. A conductive pattern(214) is interposed between the solder mask and the semiconductor chip. One side of the conductive pattern covers the respective windows on the insulating layer to be connected to the chip pad. The other side of the conductive pattern is coupled to the metal foil to be connected to the solder ball through the penetration hole formed in the outer portion. A molding compound(206) seals the side surface of the semiconductor chip, including the conductive pattern.
申请公布号 KR20010046832(A) 申请公布日期 2001.06.15
申请号 KR19990050754 申请日期 1999.11.16
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, SIN
分类号 H01L23/28;(IPC1-7):H01L23/28 主分类号 H01L23/28
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