| 摘要 |
PURPOSE: An enable signal generation circuit of a data switch control signal of a memory device is provided to prevent the generation of a fail by minimizing a delay time required in activating a QFCB enable signal. CONSTITUTION: The circuit includes a NAND logic part(100), a driving part and a latch(102). If a write command(wt_cmd) sychronized to a clock(clk) is applied, a write command recognition signal(casp6_qfc) is made in a command decoder, and this signal is transferred to a NOR gate(1199) of the NAND logic part and activates a QFCB enable signal(wt_qfcenb) through the driving part and the latch part. Then, if wt0,wt1,wt2 and wt3 are from the NAND logic part, a signal activated as long as a burst length is output, and this signal is disabled, the QFCB enable signal is disabled. The driving part drives an output of the NAND logic part, and the latch latches an output of the driving part.
|
