| 摘要 |
Even input bit lines, a first latch circuit group and a second latch circuit group are provided in a logical circuit. The first latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a first timing. The second latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a second timing. The output ends of a plurality of latch circuits are wired-OR to a first node, the plurality of latch circuits latching signal bits which propagate one half of the even input hit lines. The output ends of a plurality of latch circuits are wired-OR to a second node, the plurality of latch circuits latching signal bits which propagate remaining one half of the even input bit lines. The first and the second nodes, are wired-OR to a third node.
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