| 摘要 |
<p>A register arrangement that enables a host CPU to optimize its accesses to registers in a network interface in order to reduce the impact of such accesses on the CPU performance. Registers that must frequently be read by the CPU are combined into a first group and assigned with consecutive addresses corresponding to one end of the register address range. Registers that must frequently be written by the CPU are grouped into a second group and assigned with consecutive addresses corresponding to the opposite end of the register address range. Registers that must frequently be both read and written by the CPU are combined into a third group and assigned with consecutive addresses between the addresses of the first group and addresses of the second group.</p> |
