| 摘要 |
<p>Source and drain regions (6, 7) of field effect transistors are fabricated with an electrically insulating layer (8, 9) formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation (5) partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. In one embodiment for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body (3) and these surfaces are on opposite sides of a channel region of each transistor. One embodiment contains two transistors having a common output region.</p> |
