发明名称 CHIP PACKAGE WITH MOLDED UNDERFILL
摘要 <p>An integrated circuit chip package (10) includes a chip (12) mounted on a substrate (14) by solder bumps and a reflow process. At least one standoff is located between the chip (12) and the substrate (14) to maintain a distance between the chip (12) and the substrate (14) during the reflow process. A mold compound (16) is used for underfilling air gaps between the chip (12) and the substrate (14). The chip package (10) is formed by placing the chip (12) and substrate (14) within a mold cavity and pressing a transfer mold compound (16) into the cavity. Air spaces between the chip (12) and substrate (14) are underfilled by the mold compound (16) as it is pressed in between the chip (12), standoffs and substrate (14). Air is allowed to escape from between the chip (12) and substrate (14) during the underfilling through a vent (26) extending through the substrate (14). The underfilling material (16) may be used to encapsulate the chip (12) at the same time underfilling is performed.</p>
申请公布号 WO0143518(A1) 申请公布日期 2001.06.14
申请号 WO2000US32438 申请日期 2000.12.07
申请人 HESTIA TECHNOLOGIES, INC. 发明人 WEBER, PATRICK, O.
分类号 H01L21/56;H01L23/31;(IPC1-7):H05K7/06;H01L23/12 主分类号 H01L21/56
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