| 摘要 |
A data processor (1) executes a specific load instruction, and a converter circuit (42) converts integer data, whose bit length is shorter than the bit length of a floating-point register, into the floating-point data, which is loaded into the floating-point register. The bit length of the integer data is specified in an integer data bit length information area of the specific load instruction. In accordance with the results decoded by an instruction control circuit (2), the conversion circuit (42) expands the bit length depending on the difference in bit length between the integer data and the mantissa of the floating-point format and converts the integer data into the floating-point data. Since there is no need for referring to the register setting to obtain the bit length information on integer data required for such conversion, a single instruction is sufficient to load data involving the conversion even in the case of conversion of data of different bit lengths. The access to the register each time the bit length of integer data changes is thus eliminated, increasing data processing efficiency.
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