| 摘要 |
PURPOSE: A semiconductor memory circuit is provided to reduce test time by testing a memory cell of all addresses by only one test in a test for determining a normal operation. CONSTITUTION: Y-predecoder(2) receives an upper Y-address signal, and generates a bank selection signal. An enable controller(3) receives a bank selection signal of the Y-predecoder and a pulse signal of a high potential, and enables each bank. A fuse ROM(1) receives a lower address signal and a redundant cell test signal, and enables a redundant cell selection signal for enabling each column of a redundant cell. The Y-predecoder(2) and the fuse ROM(3) fix a bank selection signal of a specific bit and many redundant cell selection signal according to Y-address signal of a high potential when testing a redundant cell to the same value, and simultaneously enable all redundant cells.
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