发明名称 |
INTERFACE FOR A MEMORY UNIT |
摘要 |
An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.
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申请公布号 |
WO0142926(A1) |
申请公布日期 |
2001.06.14 |
申请号 |
WO2000US33036 |
申请日期 |
2000.12.06 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
OBERLAENDER, KLAUS;RANDHAWA, SABEEN;MARTELLONI, YANNICK;HENFTLING, MANFRED;ZEMACH, RAMI;PELEG, ZOHAR;WIEDHOLZ, CHRISTIAN;BAROR, GIGY;SHOHAM, DORON;TRAININ, ODED;MARGALIT, NIV |
分类号 |
G06F12/02;(IPC1-7):G06F12/02 |
主分类号 |
G06F12/02 |
代理机构 |
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