| 摘要 |
PURPOSE: A writing recovery circuit is provided to prevent the wrong operation of a chip by using a writing control signal instead of using an address transition detection signal, by providing a device for quickening an equalization timing of a bit line and a data line, thereby rapidly recovering the bit line and the data line after a writing cycle. CONSTITUTION: The first NOR gate(NOR1) performs a NOR combination of the second writing control signal(WCDN) and input data(DATA IN). The first inverter(I1) inverses signals of the input data(DATA IN). The second NOR gate(NOR2) performs a NOR combination of the second writing control signal(WCDN) and the signal inversed from the first inverter(I1). The second and the third inverter(I2, I3) respectively inverse signals outputted from the first and the second NOR gate(NOR1, NOR2). A NAND gate(NG1) performs a NAND combination of the first and the second writing control signal(CWEN, WCDN). The fifth inverter(I5) inverses an output of the NAND gate(NG1). The sixth and the seventh inverter(I6, I7) respectively inverse an output of the fifth inverter(I5). An equalization control unit(20) outputs a bit line equalization signal(BLEQ-E) and a data line equalization signal(DLEQ-E). The first and the second transmission gate(TG1, TG2) respectively apply an output of the second and the third inverter(I2, I3) to a data line equalization unit(16).
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