CELL BLOCK SELECTION DECODER OF MEMORY

摘要

PURPOSE: A cell block selection decoder of a memory is provided to reduce a layout area by making a decoder size different according to a position of a cell block, and reduce a current. CONSTITUTION: A cell block selector(300) receives a predetermined address signal, and generates a selection signal. A cell core(400) includes a cell block that is enabled by a selection signal of the cell block selector, and inputs/outputs a predetermined data according to a word line control signal, a sense signal and a write control signal. The selector includes an inverter. The inverter(INV20-INV35) includes NAND gate(N0-N15) and NMOS transistor(NM). The NAND gate(N0-N15) has a big size in proportion to a driving distance, and performs NAND operation to a predetermined address. The NMOS transistor(NM) is connected in parallel to PMOS transistor(PM) that receives a low potential output signal of the NAND gate(N0-N15) through its own gate and applies a power voltage to an output terminal. Here, the NMOS transistor(NM) is sequentially connected to the PMOS transistor(PM) in proportion to a driving distance. The NMOS transistor(NM) receives a high potential output signal of the NAND gate(N0-N15) to the contact point through its own gate, and outputs ground voltage to an output terminal.