Phase modulated reduction of clock wander in synchronous wide area networks

摘要

A phase detector for controlling a phase locked loop having a voltage controlled oscillator. A counter is clocked by a clock signal produced by the voltage controlled oscillator. A latch coupled to the counter is clocked by a modulated clock signal to latch values output by the counter. The modulated clock signal is produced by a phase modulator which modulates a synchronization clock reference signal. An accumulator coupled to the latch and clocked by the modulated clock signal receives and averages the latch values to produce a phase error signal representative of phase difference between the voltage controlled oscillator clock signal and the synchronization clock reference signal. The phase error signal is coupled to the voltage controlled oscillator to reduce the phase difference. The phase modulator modulates a rising edge of the synchronization clock reference signal with a modulation signal having modulation frequencies outside the loop bandwidth of the phase locked loop. The modulation signal is a discrete step signal having a fine time resolution which causes the latch to latch different values output by the counter in different time intervals corresponding to the time of occurrence of the modulated clock signal's rising edge with respect to the respective time intervals.