SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR SYNCHRONIZING INTER-CHIP STORAGE PART

摘要

PROBLEM TO BE SOLVED: To accelerate inter-chip corresponding processing rate by transferring data between chips. SOLUTION: A CPU chip module 10 is provided with a display data RAM 21 to be accessed by being designated by an address in a prescribed address range, a CPU 24 connected via a bus 27 with the RAM 21 for performing access via the bus 27 to the RAM 21, and a data transfer interface 23 connected with the bus 27 for judging that the designated address is within the prescribed address range, based on a signal on the bus 27 and outputting an address obtained by modifying the designated address and data on the bus 27 to the outside part. A peripheral chip module 30 is provided with a display data RAM 31 to be accessed by being designated by the address in the prescribed address range and a data transfer interface 33 which is connected via a bus 37 with the RAM 31 for address-designating the RAM 31 by the address transferred from the outside and performing access to the RAM 31.