| 摘要 |
PROBLEM TO BE SOLVED: To reduce an occupancy area in a chip, to shorten lockup time and to be strong against disturbance even when an oscillation frequency band is wide and a multiplying factor change range is wide. SOLUTION: For this synchronization method of a phase locked loop, in a PLL for smoothing a control current IC made to flow out or flow in from a charge pump 13 based on an up clock/UCK or a down clock DCK supplied from a phase frequency comparator 11 in an LPF 14, turning it to a control voltage, oscillating an internal clock CKI provided with an oscillation frequency corresponding to the control voltage of an oscillation frequency band based on oscillation frequency band setting data DTF in a VCO 15, frequency-dividing the internal clock CKI by a frequency dividing ratio N based on multiplying factor setting data DTD in a frequency divider 16 and outputting it as a frequency divided clock CKD, the value of the control current IC is changed based on the oscillation frequency band setting data DTF and the multiplying factor setting data DTD. |
