Apparatus having a flattener for outputting aligned or unaligned information from an instruction execution pipeline

摘要

An integrated circuit (12) includes a processor (17) having an instruction execution pipeline (22). The pipeline has a plurality of successive stages (26-42) which correspond to respective successive phases of instruction execution. Instructions being executed move successively through the stages (26-42). A flattener section (18) is provided in the integrated circuit (12), and holds the state of certain pipeline signals until subsequent points in time. This permits various signals generated at different points in time during execution of an instruction to all be simultaneously available at a later point in time. A selector section (19) of the integrated circuit (12) selects either the output of the flattener section (18) or certain pipeline signals to be exported off the integrated circuit.