Semiconductor memory device having read/write amplifiers disposed for respective memory segments

摘要

Segment selection circuits 40A are arranged adjacent read/write amplifiers 20. When one of the segments 0 to 7 in a memory cell array 10 is selected by a signal on segment address lines CA8 to CA6, a read amplifier 21 or a write amplifier 22 of the read/write amplifier 20 corresponding to the selected segment is activated in response to activation of a signal on a read timing signal line RT or a write timing signal line WT. The lines CA8 to CA6, RT and WT are arranged along the row of the segment selection circuits 40A.