| 摘要 |
PROBLEM TO BE SOLVED: To secure sufficient margin for these time and to shorten an access time without increasing chip size even in an internal access time when various input signals are inputted in a system clock with the prescribed setup and hold time. SOLUTION: A semiconductor memory in which a system clock input, an address inputted synchronizing with a rise edge of this clock, and a control signal exist, is constituted so that input data in which latch is performed by a rise edge of a system clock are held by a latch signal formed by the logical sum of a system clock and data input control signals generated by input of various control signals RAS, CAS, CS, and the like.
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