发明名称 INTEGRATED CIRCUIT COMPRISING TEST CIRCUIT AND TEST METHOD FOR IT
摘要 PROBLEM TO BE SOLVED: To provide a test means for an integrated circuit which dynamically specifies a trigger condition and sampling timing. SOLUTION: An integrated circuit 100 comprises a target circuit 102 and a test circuit 104. The target circuit 103 uses a clock signal 101 to transfer a target signal 103 in the integrated circuit 100. The test circuit 104 samples the target signal 103 at a timing selected among a plurality of possible timings in the clock cycle of the lock signal 101. The test circuit 104 samples the target signal 103 in response to a test signal 105 representing the selected timing.
申请公布号 JP2001159664(A) 申请公布日期 2001.06.12
申请号 JP20000308744 申请日期 2000.10.10
申请人 HEWLETT PACKARD CO <HP>;AGILENT TECHNOL INC 发明人 DON D JOSEPHSON
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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