| 摘要 |
The semiconductor memory device is provided with an address buffer. The address buffer includes address input circuits provided for respective bits of an address signal. Each address input circuit includes an address signal transmission circuit that is activated by an activation signal, a plurality of delay circuits provided in parallel, each delaying and outputting the output of the address signal transmission circuit, and a delay time select circuit that selects an output signal from one of the plurality of delay circuits according to the type of access and transmits the selected signal to an address decoder. Each of the plurality of delay circuits has a delay time different from each other. If an access is started with activation of the address buffer, a delay time that is shorter than a conventional case is set.
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