Method of manufacturing a split-gate flash memory cell with polysilicon spacers

摘要

A method of manufacturing a self-aligned split-gate flash memory cell with high coupling ratio is disclosed. A polysilicon spacer is first formed on each of the inner walls between the two select gates on which a dielectric layer is formed. A drain and a source are next formed adjacent to each of the outer walls of the two select gates and between the two polysilicon spacers, respectively. A silicon oxide layer is deposited. A predetermined thickness of the silicon oxide layer is then removed and the dielectric layer is removed down to a predetermined thickness by using a dry etching process. Finally, a control gate is formed above the polysilicon spacers.