发明名称
摘要 In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including a number of memory cells each having a floating gate and a control gate, an interlayer insulator film is formed to cover the control gate of the memory cells in the memory zone and a gate electrode formed in the peripheral circuit zone. A contact hole is formed through the interlayer insulator film to reach the gate electrode formed in the peripheral circuit zone, and is filled with a first conducting material. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate of a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line. A second conducting material is deposited on the interlayer insulator film to completely fill up the groove so that a plate-shaped contact is formed in the groove, and a layer of the deposited second conducting material is patterned to an overlying interconnection extending on the interlayer insulator film along the word line. Thus, the word line is electrically connected to the overlying interconnection in parallel over the whole length of the word line, through the plate-shaped contact, which has a bottom surface contacted with the word line over the whole length of the plate-shaped contact and which is integral with the overlying interconnection over the whole length of the plate-shaped contact. Therefore, the resistance of the word line is reduced without complicating the fabricating process, so that the reading time can be shortened.
申请公布号 JP3175705(B2) 申请公布日期 2001.06.11
申请号 JP19980263834 申请日期 1998.09.18
申请人 发明人
分类号 H01L21/3205;H01L21/768;H01L21/8242;H01L21/8247;H01L23/522;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 H01L21/3205
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