发明名称 MEMORY BUS ACCESS CONTROL SYSTEM AFTER CACHE MISS
摘要 PROBLEM TO BE SOLVED: To improve access efficiency to a main memory by limiting access to an outside main memory in a microprocessor having a cache memory. SOLUTION: This information processor is provided with instruction fetch parts 410 and 411 for fetching both instruction systems at the sequential side and target side of a branch instruction, cache controlling parts 54 and 56 for fetching instructions from a cache memory 52 or a main memory 64 in response to a fetch request from the instruction fetch part, a memory bus access part 60 for performing access to a main memory, and instruction buffers 470 and 471 for holding the fetched instructions. Moreover, this information processor is provided with branch predicting parts 430 and 431 for operating the branch prediction of the branch instruction stored in the instruction buffer prior to the execution of the branch instruction. When the branch direction of the branch instruction is uncertain, the cache controlling parts 54 and 56 control the memory bus access to the main memory 52 after cache miss.
申请公布号 JP2001154845(A) 申请公布日期 2001.06.08
申请号 JP19990341014 申请日期 1999.11.30
申请人 FUJITSU LTD 发明人 TAKO SHINICHIRO;KAMIGATA TERUHIKO;SUGA ATSUHIRO;OKANO HIROSHI;TAKEBE YOSHIMASA;SATO TAIZO;YAMAZAKI YASUHIRO;YODA HITOSHI
分类号 G06F9/38;G06F9/32;(IPC1-7):G06F9/38 主分类号 G06F9/38
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