| 摘要 |
PURPOSE:To attain the high speed of the addition/subtraction of a floating point number by executing normalization processing and rounding processing in parallel. CONSTITUTION:A rounding correction determination circuit 8 provided with plural rounding correction judgement circuits 81 corresponding to each of plural rounding position candidates and a selection circuit 82 to select the output of the rounding correction judgement circuits 81 in conformity with the output of a rounding position determination circuit 6 is provided. In this configuration, the output of an adder/subtracter circuit 4 is used as the inputs of the rounding position determination circuit 6, the rounding correction determination circuit 8, and a rounding correction addition circuit 10. Thus, since the adder/subtracter circuit 4 and the rounding correction judgement circuit 81, and the rounding correction addition circuit 10 and a normalized shift number calculation circuit 12 come to be capable of executing the processing simultaneously, the processing time of a whole arithmetic unit is shortened, and the high speed of a arithmetic processing is attained. |
