| 摘要 |
PROBLEM TO BE SOLVED: To provide the layout method of a semiconductor integrated circuit. SOLUTION: There are provided an automatic arrangement processing step for arranging a circuit element on a semiconductor substrate, an automatic wiring processing step for connecting wiring between the circuit elements, based on circuit connection information and the arrangement result of the automatic arrangement processing step, a wiring resistance capacity extraction processing step calculating the wiring resistance of wiring and wiring capacity and storing them in a net list as a total resistance and total capacity, a multilayer parallel wiring processing step for scanning the upper/lower wiring layers of wiring with respect to wiring which does not satisfy restricting conditions as the permission range of wiring delay time calculated, based on the resistance of wiring and the capacity of wiring and arranging a wiring graphic constituting resistance and capacity in an idle wiring region and the decision processing step of restriction violation for deciding whether the restriction condition is satisfied.
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