| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that it is required to insert a clock delay circuit and adjust a timing so as to optimize a sampling timing in an A/D converter in the case of a pulse detection system. SOLUTION: This PLL circuit is constituted by providing a phase error detection circuit 12 provided with a temporary judgment device 11 for temporarily judging input data to the A/D converter 11 as the respective levels of 1, 0 and -1, a pattern detector 14 for checking a transition pattern from the data of one clock before to the present data in signals inputted based on the judged result and instructing a selector 15 to select the output data of the A/D converter 24 when a specified pattern is detected and the selector 15 for selecting phase error data from the output of the A/D converter 24 corresponding to the instruction of the pattern detector 14, converting them into a current and outputting it as an error current.
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