Semiconductor memory device, such as synchronous dynamic random access memories (SDRAMs), includes equalizing circuit for equalizing the potentials of the data transmission line pairs

摘要

Synchronous dynamic random access memories (SDRAMs) have problems associated with unstable readability when operating at high speeds, and in addition problems with complicated layout and high current demand. The proposed design includes switch-element pairs connected between the data transmission pairs and the input/output node pair of the pre-amplifier, and are made conducting in a pulse-manner during a given time so as to provide a potential difference which is generated between the data transmission pairs for the input/output node pair of the pre-amplifier. A transmission circuit is provided for transmitting the pre-amplifier output signal to the outer face.