APPARATUS FOR AND METHOD OF IMPLEMENTING VITERBI DECODING

摘要

The invention is directed to an apparatus for and method of implementing a Viterbi decoder utilizing analog processing. In a preferred embodiment of the invention, an analog Viterbi decoder is provided for a long constraint-length (e.g. K >/= 7) convolutional code having a high level (e.g., 64 or more) of states. In accordance with a preferred embodiment of the invention, an analog Viterbi decoder includes an add-compare-select (ACS circuit module that is preferably implemented by a number (e.g. 64) of parallel ACS processors corresponding to each state-n of the decoder used to accumulate path metrics. A plurality of branch metric calculation (BMC) units are used to convert received code words into an appropriate analog format for use by the ACS processors. The ACS module selects the "best" path metrics for output to and storage in a survivor path memory module to produce the decode (destination) information bits. The analog processing utilizing to implement the Viberti decoder produces a high speed, area-efficient, low power decoding technology that is capable of fabrication on a single integrated circuit.