A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
申请公布号
WO0141199(A1)
申请公布日期
2001.06.07
申请号
WO2000US29001
申请日期
2000.10.18
申请人
INTEL CORPORATION;MIELKE, NEAL, R.;FAZIO, ALBERT;PARAT, KRISHNA;WADA, GLEN;STONE, REX
发明人
MIELKE, NEAL, R.;FAZIO, ALBERT;PARAT, KRISHNA;WADA, GLEN;STONE, REX