MICROPROCESSOR ARRANGEMENT HAVING AN ENCODING FUNCTION

摘要

The invention relates to a microprocessor arrangement comprising a data bus (4) for transmitting data between functional units (1, 2, 3). Each unit contains an encoding/decoding device (11, 21, 31) on the bus side. Said devices are controlled by a random-check generator (6) in a synchronous manner. The arrangement allows for a relatively high security against bugging the data which is transmitted by means of the data bus, whereby additional switching requirements are justifiable.