| 摘要 |
A multiplexing arrangement for transferring data retrieved from a memory array to data outputs of a semiconductor memory, including a multiplexing circuit that is responsive to latency select signals to cause data retrieved sequentially from the memory array to be loaded into and read from data latch circuits of a data output register in a sequence that establishes a known delay between the time that data is retrieved from the memory array and stored in the data output register and the time that the data is read from the data output register. The delay allows data to be held in the data output register when the data is available and to be passed to the data outputs of the memory when desired. Also described is a multi-phase timing signal generator that includes a multi-stage shift register connected for operation as a recirculating shift register, a drive circuit responsive to system clock pulses for advancing a bit pattern through the shift register, and an output circuit for logically combining signals provided at outputs of the shift register as the bit pattern is advanced through the shift register to produce sequential timing signals.
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