| 摘要 |
The present invention relates to a pin configuration in a highly integrated memory chip; and, more particularly, to a CSP pin configuration which is compatible with a TSOP pin configuration. A CSP semiconductor device according to the present invention comprises: a die pad area formed in the middle of a semiconductor chip; a first ball pad area allocated at a left side of the die pad area, having a ball array having first and second columns; and a second ball pad area allocated at a right side of the die pad area, having a ball array having first and second columns, wherein the first ball pad area includes ball pads which are positioned at a right side of a corresponding TSOP, wherein the second ball pad area includes ball pads which are positioned at a left side of the corresponding TSOP, wherein the first column of the first ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of lower priority, and the second column of the first ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of lower priority, and wherein the first column of the second ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of higher priority, and the second column of the second ball pad area includes odd number pins of the TSOP, which are disposed in order of higher priority.
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