发明名称 WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <p>PURPOSE: A wafer level package is provided to improve reliability of a solder junction of the package, by using a material having a low modulus of elasticity and electro-conductivity to reduce the stress concentrated on a bump. CONSTITUTION: A chip pad(52) is formed in a semiconductor chip(50). A lower insulating layer(54) is formed in the upper portion of the semiconductor device to expose the upper surface of the chip pad. A metal interconnection(56) is formed in the upper portion of the lower insulating layer so that one end of the metal interconnection is connected to the chip pad. An upper insulating layer(58) is formed in the upper portion of the metal interconnection to expose the upper surface of the other end of the metal interconnection. A buffer pad(60) is formed in the other end of the metal interconnection, and is made of a material of a low modulus of elasticity wherein the material has electro-conductivity. A bump(62) is made by adhering a solder ball to the buffer pad.</p>
申请公布号 KR20010045916(A) 申请公布日期 2001.06.05
申请号 KR19990049435 申请日期 1999.11.09
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KANG, IN SU
分类号 H01L23/48;(IPC1-7):H01L23/48 主分类号 H01L23/48
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