| 摘要 |
PURPOSE: A data detector is provided to simplify a detection of a data threshold varied by every frequency for reducing a circuit area and a detection time delay so that it can reduce delay time. CONSTITUTION: The circuit comprises the first multiplexor(21), the second multiplexor(22), an addition block(200), the first register(25), the second register(26), the third multiplexor(27), the third register(28), the first OR gate(29), and the second OR gate(30). The first multiplexor(21) multiplexes n bit reference threshold and m bit prior value, and outputs m bit data. The second multiplexor(22) multiplexes m bit current value and inverted n bit data, and outputs m bit data. The addition block(200) includes an m-n bit adder(23) and an n bit adder(24). The m-n bit adder(23) adds the n-m bit data generated by the first multiplexor(21) and the second multiplexor(22). The n bit adder(24) the n bit data generated by the first multiplexor(21) and the second multiplexor(22). The first register(25) stores the n-m bit data and the n bit data output by the addition block(200). The second register(26) stores the n-m bit data resulted from inverting the n-m bit data of the n-m adder(23), and the n bit data resulted from inverting the n bit data of the n adder(24).
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