发明名称 Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel
摘要 Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.
申请公布号 US6243031(B1) 申请公布日期 2001.06.05
申请号 US20000528659 申请日期 2000.03.20
申请人 MARVELL INTERNATIONAL LTD. 发明人 JUSUF GANI;SUTARDJA PANTAS
分类号 G11B20/10;H03K5/00;H03K5/13;H03L7/081;(IPC1-7):H03M5/06 主分类号 G11B20/10
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