| 摘要 |
PURPOSE: An analog-digital delay locked loop(DLL) combining a voltage controlling oscillator and a shift register-type delay locked loop is provided to enable a fast locking of digital delay locked loop and to satisfy small jitter characteristics of analog delay locked loop. CONSTITUTION: In an analog-digital delay locked loop(DLL), a first delay model produces a delayed clock signal(clk_d) of a clock signal(clk). A controller(120) produces a reproduction enable signal(rep_en) responding to an enable signal(en). A voltage controlling oscillator(130) produces a measuring oscillation signal(m_osc) responding to a second delay clock signal(clk_d2), the second delay signal(clk_2) and a voltage control signal(vcon). A reproduced-voltage controlling oscillator(140) produces a reproducing oscillation signal(r_osc) responding to a reproduction signal(/replica), the reproduction enable signal(rep_en) and the voltage control signal(vcon). A digital delay locked loop(150) produces a delay locked loop clock signal(dll_clk) responding to signals(/replica,clk2,/clk_d2,m_osc,r_osc). A second delay mode(160) produces a comparison clock signal(comp_clk). A phase detector(17) produces an up signal(up) or a down signal(down) by comparing the phase differences between the clock signal(clk) and the comparison signal(comp_clk). A charge pump(180) produces the voltage control signal(vcon) responding to the up or down signals(up,down). A loop filter(190) eliminates high frequency noises from the voltage control signal(vcon).
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