| 摘要 |
PURPOSE: A method for manufacturing a capacitor is provided to increase efficiency of an exposure process and an overlay process, by generating a step for performing an align in the exposure process for forming a storage node electrode. CONSTITUTION: An interlayer dielectric(22) is deposited on the entire substrate(10) and a contact hole is formed in the interlayer dielectric. A conductive material is filled in the contact hole and patterned to form in a cell region a contact plug and a bit line connected to an active region. An interlayer dielectric(26) is formed and planarized to form a contact hole in the interlayer dielectric formed in the cell region and a scribe line region. A spacer composed of an insulating material is formed on the inner sidewall of the contact hole. A conductive layer is filled in the contact hole and planarized to form in the cell region a contact plug for a storage node electrode while a conductor contact plug is formed in the scribe line region. The conductor contact plug is selectively removed while leaving the spacer in the contact hole of the scribe line region. A conductive material and a ferroelectric layer are deposited. A photolithography process is performed by using a step of the structure resulting from the contact hole of the scribe line region as an align mask. The ferroelectric layer and the conductive material are patterned to form in the cell region a storage node electrode and a dielectric thin film connected to the contact plug.
|
