| 摘要 |
A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.
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