| 摘要 |
PURPOSE: A signal transfer apparatus is provided to reduce an area of a semiconductor memory by reducing the number of address(or data) transfer lines and the number of relays to the number of them as to two signals, by enabling one decoded output signal or restoring it to the original address(or data). CONSTITUTION: The apparatus includes an address offset circuit(100) comprising: the first offset unit endowing an offset to a reference signal by controlling the reference signal to pass through different delay path respectively according to the value of the first input address signal; the second offset unit endowing an offset by controlling an output signal of the first offset unit to pass through different delay path respectively according to the value of the second input address signal; and the third offset unit endowing an offset by controlling an output signal of the second offset unit to pass through different delay path respectively according to the value of the third input address signal. Each offset unit includes: the first transfer gate(P10) transferring the inputted reference signal to the first output terminal when the input address signal has a 'LOW' voltage level; the second transfer gate(N10) transferring the inputted reference signal to a delay circuit part when the input address signal has a 'HIGH' voltage level; and a switching device transferring an output signal of the delay circuit part to the first output terminal when the input address signal has a 'HIGH' voltage level.
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