发明名称
摘要 PURPOSE:To reduce delay between a CPU for executing emulation and a target system and to delay between the CPU and the control circuit of the incircuit emulator and to enable real-time emulation even at a high clock frequency by forming specified wiring connection. CONSTITUTION:The device is equipped with first terminals 4 having the same arrangement as the CPU for executing emulation, second terminals 5 arranged in various directions so as not to block the first terminals 4, first wiring 6 to connect the first terminals 4 and a first chip 2, second wiring 7 to connect the first terminals 4 and a second IC chip 3, third wiring 8 to connect the first terminals 4 and the second terminals 5. Further, the device is equipped with a fourth wiring 9 to connect the second terminals 5 and the first IC chip 2, fifth wiring 10 to connect the second terminals 5 and the second IC chip 3, and sisth wiring 11 to connect the first IC chip 2 and the second IC chip 3.
申请公布号 JP3173055(B2) 申请公布日期 2001.06.04
申请号 JP19910225555 申请日期 1991.09.05
申请人 发明人
分类号 G06F11/22;G06F15/78;H01L23/538 主分类号 G06F11/22
代理机构 代理人
主权项
地址