| 摘要 |
The object is to enable implementation of the CDMA complex QPSK spread modulation, which can be operated on a reduced gate scale with a reduced power consumption. Digital data signals Di and Dq are spread modulated by multipliers 11 and 12, with the first spreading codes Ci and Cq generated from spreading code generators 31 and 32, so as to produce spread modulated signals (Di.Ci) 41 and (Dq.Cq) 42. Signals 41 and 42 are input to a complex QPSK processor 13 where they are subjected to the complex QPSK operation with the second spreading codes Si and Sq generated from spreading code generators 33 and 34. The resultant signals are filtrated through LPFs 18 to 21. DACs 22 to 25 convert the filtrated signals into analog values 51 to 54. Signals 44 and 45 including the ICH data signal Dq are processed through multipliers 26 and 27 so as to weight them with a gain factor G from a gain factor controller 63. <IMAGE> |
