| 摘要 |
PURPOSE: A vector quantizer of a binary tree structure is provided to reduce a distance calculation by employing a distortion processor module(DMP) having a simple structure. CONSTITUTION: A counter(100) generates a counter signal(101). A test vector unit(210) generates a test vector signal(219) in response to the counter signal(101). A code vector unit(220) generates a code vector signal(229) in response to the counter signal(101). A multiplexer(250) receives the test vector signal(219) from the test vector unit(210), the code vector signal(229) from the code vector unit(220), and a demultiplexing signal(501) to output a multiplexing signal(251). In response to select signals(SEL1,SEL2) provided from an external, a multiplexer(290) multiplexes the multiplexing signal(251) provided from the multiplexer(250). A first arithmetic logic unit(310) receives an input data signal(299) and the code vector signal(229), performs a subtraction on the two signals(299,229), and outputs a first arithmetic logic signal(311) corresponding to an absolute value of the subtraction result. A square unit(320) receives and squares the first arithmetic logic signal(311) to output a square signal(321). A second arithmetic logic unit(330) receives the square signal(321) through a first input terminal and a mean square error signal(301) through a second input terminal to output them. A first delay(410) delays the mean square error signal(301) for a predetermined time to output a first delay signal(411). A comparator(420) compares the mean square error signal(301) with the first delay signal(411) to generate a logic signal(401). A demultiplexer(500) demultiplexes the logic signal(401) and provides a demultiplexing signal(501) to the multiplexer(250). A serial-to-parallel converter(610) converts the received logic signal(401) from serial into parallel. A second delay(620) receives parallel data from the serial-to-parallel converter(610), stores the parallel data for a predetermined time, and generates an address signal(699).
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