Data buffer control circuits, integrated circuit memory devices and methods of operation thereof using read cycle initiated data buffer clock signals

摘要

A data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. A clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. A clock buffer control circuit is responsive to the read cycle control signal and to the clock signal and transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval. A first half cycle of the input clock signal may commence with the first transition of the input clock signal, and the clock buffer control circuit may be operative to transition the clock buffer control signal to the first state following the first transition of the input clock signal and before the end of the first half cycle of the input clock signal.