发明名称 WAFER FLATTENING PROCESS
摘要 A wafer flattening process for improving the micro-roughness of a wafer by local etching while maintaining a distance between a plasma discharge location and the wafer surface at a predetermined value. By executing a plasma generating step, SF6 gas in a gas cylinder 31 is fed to the inside of an alumina discharge tube 2, then plasma discharge of the SF6 gas is caused by a plasma generator 1 to produce an activated species gas G and which is locally sprayed from a nozzle portion 20 of the alumina discharge tube 2 to the surface of the silicon wafer W. In this state, by performing a local etching step, the surface of the silicon wafer W is flattened. At this time, the distance from the approximate center of the plasma discharge location to the surface of the silicon wafer W is set to a distance larger than 3000 times the mean free path of the ions in the activated species gas G and smaller than 6000 times. Due to this, the ions in the activated species gas G are extinguished before being sprayed from the nozzle portion 20 and therefore the surface of the silicon wafer W is etched by only the neutral radicals without being damaged.
申请公布号 US2001002336(A1) 申请公布日期 2001.05.31
申请号 US19990392131 申请日期 1999.09.08
申请人 YANAGISAWA MICHIHIKO;SADOHARA TAKESHI 发明人 YANAGISAWA MICHIHIKO;SADOHARA TAKESHI
分类号 H01L21/302;C23F4/00;H01L21/3065;H05H1/46;(IPC1-7):H01L21/302 主分类号 H01L21/302
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