| 摘要 |
A semiconductor apparatus (010) is disclosed that includes a gate electrode formed over an active area and isolation area that can address adverse current properties that may result in a subthreshold "hump" in a gate voltage (VG)-drain current (ID) response. A first embodiment (010) may include an active area (016) formed adjacent to an isolation area (018). A gate insulator (014) may be formed over active area (016). A gate electrode (020) can be formed over an active area (016) and an isolation area (018). A gate electrode (020) may include end portions (020a) formed in the vicinity of an active area (016)/isolation area (018) interface, and a central portion (020b) formed between end portions (020a). End portions (020a) may be doped differently than a central portion (020b) to effectively compensate for lower threshold voltages in such areas. End portions (020a) may be doped to a conductivity type that is different than a central portion (020b) and the same as a channel region. Alternatively, end portions (020c) may be doped to a conductivity type that is the same, but lower in concentration than a central portion (020b), and different than a channel region conductivity type.
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