ELECTRONIC PHASE-LOCKING LOOP (PLL)

摘要

The invention relates to an electronic phase-locking loop (PLL) with a digital configuration. A supplementary analogue phase detector (APD) with which the phase error ("jitter") can be damped even more effectively than before is added to said phase-locking loop. The inventive PLL is especially suitable for use as an integrated circuit (IC) in service-integrated communications networks (ISDN), data communications or networks.